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Digital clock
Description and schematic of a complete digital clock.
How it works
The IC 555 is used here (as already seen with the LED-Flasher) as an astable oscillator giving frequency of 1.000 Hz at its output
(R1: 1 M, R2: 220 k, C1: 1 µ). This signal is put to the clock gate of IC 6 and IC 7.
IC 6 and IC 7 are BCD-counters cascaded to count up to 99. This is
unwantend, so IC 10 (4 x NAND) is used to prevent this by resetting the counters if BCD code 0110 0000 (=60) occurs at their
output pins. If a reset occurs, a clock signal is sent to the next counter stage (IC 5 and IC 4, for the hours).
The next counters (IC 4 and IC 5) are incremented by one, if the
first counter stage reaches 60 and is reset instantly. The second counter stage is also cascaded to count up to 99, but is
reset by the NAND IC 10 if BCD-code 0110 0000 (=60) occurs at their output pins. Then, a clock signal is sent to the third
stage, counting the hours.
Same thing here, but this time, the counters IC 2 and IC 3 should
only count up to 23, so a reset must be achieved if BCD-code 0010 0100 (=24) occurs at their output pins.
The ICs 8, 9, 11, 12, 13 and 14 are used to decode the BCD-code provided
by the counters and to drive the 7-segment LEDs.
Setting the clock is easy: by pressing the keys, you give a clock
signal to the corresponding counter stage.
